Contact details
Old electronic contact details:
(for previous publications searching)
http://www.eee.kcl.ac.uk/~ianc
http://www.users.totalise.co.uk/~ian.g.clark/
http://www.geocities.com/igc_sparks/
igclark@iee.org
Ian.Clark@kcl.ac.uk
Ian@orion.eee.kcl.ac.uk
udee782@bay.cc.kcl.ac.uk
udee782@alder.cc.kcl.ac.uk
Address:
Electrical and Electronic Engineering,
School of Engineering,
Merz Court,
Newcastle University,
Newcastle upon Tyne,
NE1 7RU,
UK.
WWW:
http://IanGClark.net/
E-Mail:
Ian@IanGClark.net
Google Scholar Profile
For the complete version of my CV please email me.
Qualifications & awards
2000 - Ph.D. in Electronic Engineering, King's College, University of London.
1991 - B.Sc.(ENG)(HONS.) in Electronic Engineering, King's College, University of London.
Employment
July 2004 to Now - Computing Officer, Electrical and Electronic Engineering, School of Engineering, Newcastle University.
July 2001 to June 2004 - Research Associate, employed jointly between the School of Electrical, Electronic and Computer Engineering, University of Newcastle-upon-Tyne, moved from Computing Science (31/8/2002), and Senior Researcher, Digital Imaging Research Centre, Faculty of Computing, Information Systems and Mathematics, Kingston University, Moved from Department of Electronic Engineering, King's College, University of London (30/9/2001). EPSRC funded COHERENT project (COmputational HEteRogEneously timed NeTworks).
Our Research Group webpage is at http://async.org.uk/, with information about this project and others.
COHERENT proposes to construct embedded real-time systems of medium complexity as on-chip systems (SoCs) with heterogeneous timing in order to improve timing and energy efficiency of systems for portable and miniature applications in control, robotics, image processing etc. The proposed concept of a hardware-oriented architecture for such systems, called real-time networks on chip (RTNoC), will consist of computational units of maximum diversity (outside the scope of the project) and communication components from a (finite set) of generic asynchronous communication mechanisms (ACMs), which is the focus of this project. The project will deliver a design methodology for RTNoC together with a parameterised library of ACM IP blocks that will, in the longer term, allow the designer to map an application-oriented specification of the system to its implementation with maximum transparency and minimum loss of time and energy resources. It will bridge the gap between the existing (e.g. MASCOT) ideas of building distributed real-time systems and those of globally asynchronous-locally synchronous (GALS) for SoCs by investigating techniques for efficient hardware implementation of the elements of communication and multitasking support in the former, and providing a wide range of asynchrony levels, from fully synchronous to wait-free and maximally non-blocking, for the latter. This will enable the seamless composition of systems with time-driven and data-driven parts.
Apr. 1998 to June 2001 - Research Associate, Department of Electronic Engineering, King's College, University of London. EPSRC funded COMFORT Project (asynchronous COmmunication Mechanisms FOr Real-Time systems), joint project with School of Computing Science and School of Electrical, Electronic & Computer Engineering, Newcastle University.
Investigation, analysis & design of asynchronous communication mechanisms, which provide reference data communication, with NO waiting, blocking or mutual exclusion between un-synchronized independently executing processes. The analysis includes the effects of the phenomenon of metastability. These mechanisms provide a necessary form of communication within safety critical and real-time GALS (Globally Asynchronous Locally Synchronous) systems. Applications for such mechanisms include internal SoC (Systems on Chip) communication.
Nov. 1995 to Aug. 1996 - Research Assistant, Department of Electronic Engineering, King's College, University of London. Implementation of a prototype Sigma-Delta / Pulse Grouping Modulator for power Digital to Analog conversion on FPGA hardware. Interface and support hardware for demonstration and measurment purposes. This project extensively used VHDL hardware description, proprietary Atmel FPGA software and in house simulation techniques.
During Ph.D. studies
Lecturing, tutorials & lab material for parts of the 1st and 3rd year undergraduate Logic Design & Advanced Logic Design (1991-1999).
Preparation and demonstration of assembly language lab material for 2nd year undergraduate Microprocessor Systems (1991-1999).
Jointly prepared and presented lecture, tutorial & lab material for 2nd year undergraduate Digital Systems Design, mainly VHDL material (1996-1998).
Jointly prepared and presented VHDL short course in Warsaw Technical University, Poland (1997).
Prepared & jointly presented lecture, tutorial and lab material for 1st year undergraduate Introduction to Computer Systems, in the Department of Computer Science at King's College (1996-1997).
Formed part of a research team on the DIAMOND Project between King's College and British Aerospace, investigating applications and expansion (through VHDL and Petri nets) of the DIA (Data Interchange Architecture) (1994).
Academic Interests
Asynchronous communication between heterogeneously timed processes, the mechanisms and their analysis. This is sometimes also called `Atomic communication' or `Wait-Free communication'. (My asynchronous communication and atomic bibliography). The communicating processes themselves can be synchronous or asynchronous, therefore these methods can be applied to the communication problems within GALS (Globally Asynchronous Locally Synchronous) systems, and SoC (Systems on a Chip) communication. For more information see our Research Group webpage at http://async.org.uk/.
Asynchronous hardware & Metastability (including my metastability bibliography).
Petri nets. for the analysis and synthesis of asynchronous circuits.
Publications
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
2016 | 2006 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997 | 1995 | 1993
2016Fei Xia, Ian Clark. "Quantitative modelling of asynchronous variables", This Asynchronous World, July 2016, pp.305-319. ISBN: 978-0-7017-0257-1. Newcastle University.
Fei Xia, Fei Hao, Ian Clark, Alex Yakovlev and E. Graeme Chester. "Buffered Asynchronous Communication Mechanisms", Volume 70, Number 1-2 (January 2006), pp.155-170, Fundamenta Informaticae, IOS Press.
Fei Hao, Fei Xia, Graeme Chester, Alex Yakovlev, Ian G. Clark. "MATLAB Models of ACMs in Control Systems", 1st International Conference on Informatics in Control, Automation & Robotics (ICINCO-2004), INSTICC Press, pp. 54-61, Volume 3, Setubal, Portugal, 25-28 August 2004.
Guang-Yeu Luo, Fei Xia, Ian G. Clark, Albert M. Koelmans, Alex V. Yakovlev. "Simulating Heterogeneously Timed Networks in Network Simulator NS", 4th International Symposium on Communicating Systems, Networks and Digital Signal Processing (CSNDSP 2004), University of Newcastle upon Tyne, UK, 20-22 July 2004.
Fei Xia, Fei Hao, Ian G. Clark, Alex Yakovlev, E. Graeme Chester. "Buffered Asynchronous Communication Mechanisms", The International Conference on Application of Concurrency to System Design (ACSD 2004), McMaster University, Hamilton, Ontario, Canada, 16-18 June 2004.
H. Simpson, E. Campbell, F. Xia, I. Clark, A. Yakovlev, D. Shang. "Further discussions on the classification and high-level models of ACMs", Technical Report Series, NCL-EECE-MSD-TR-2004-102, School of Electrical, Electronic and Computer Engineering, University of Newcastle upon Tyne, June 2004. [pdf (233KB)].
Guang-Yeu Luo, Ian G. Clark, Fei Xia, Albert M. Koelmans, Alex V. Yakovlev. "Simulating Hets in NS for developing an ACM transport protocol for Networks-on-Chip", PREP 2004, Poster presentation, University of Hertfordshire, 5-7 April 2004.
Ian G. Clark. "Asynchronous Communication Mechanism taxonomy and classification". Paper and presentation. School of Electrical, Electronic and Computer Engineering Postgraduate Conference 2004. University of Newcastle upon Tyne. 21-22 January 2004. This paper won the Best RA Presentation prize.
F. Hao, F. Xia, I.G.Clark, A. Yakovlev, E.G. Chester. "RR-BB algorithm models in MATLAB", 15th UK Asynchronous Forum, Cambridge University, 5-6 January 2004.
G.Y. Luo, I.G. Clark, F. Xia, A.M. Koelmans, A. Yakovlev. "Simulating heterogeneous timing networks in network simulator NS", 15th UK Asynchronous Forum, Cambridge University, 5-6 January 2004.
F. Hao, A. Yakovlev, E.G. Chester, F. Xia, I.G. Clark, D. Shang. "Implementation of a three-slot signal ACM". Poster presentation at PREP 2003 - Postgraduate Research Conference in Electronics, Photonics, Communications and Software. 14-16 April 2003, University of Exeter.
Ian G. Clark, Fei Xia, Alex V. Yakovlev, Delong Shang. "Data Communication Mechanisms for Systems with Heterogeneous Timing". Invited paper at the 2003 Heterogeneous Computer Systems Workshop, University of South Australia, Adelaide. 27th February 2003. [pdf (293KB)].
Ian G. Clark. "Asynchronous Communication Mechanisms Survey". Paper and Poster presentation. School of Electrical, Electronic and Computer Engineering Postgraduate Conference 2003. University of Newcastle. 22-24 January 2003.
F. Hao, A. Yakovlev, E.G. Chester, F. Xia, I.G. Clark, D. Shang. "Implementation of a three-slot signal ACM", 13th UK Asynchronous Forum, 16-17th December 2002, University of Cambridge, Computer Laboratory. [pdf (73KB)].
Fei Xia, Alex V. Yakovlev, Ian G. Clark, Delong Shang. "Data Communication in Systems with Heterogeneous Timing", IEEE Micro, Vol. 22, Part 6 November/December (2002), pp. 58-69. [pdf (235KB)].
Fei Xia, Ian Clark. "Algorithms for Signal and Message Asynchronous Communication Mechanisms and their Analysis", Volume 50, Number 2 (2002), pp.205-222, Fundamenta Informaticae, IOS Press.
Fei Xia, Alex V. Yakovlev, Ian G. Clark, Delong Shang. "Data Communication in Systems with Heterogeneous Timing", MPCS'02, Fourth International Conference on Massively Parallel Computer Systems, sponsored by Euromicro, 10-12 April 2002, Ischia, Italy. [postscript gzip'd (101KB)].
A.C. Davies, I.G. Clark. "Asynchronous Communication without Waiting: from the Concept to the Hardware", Applied Electronics 2001 conference, Plzen, Czech Republic, 5-6 September 2001, pp 55-59. ISBN 80-7082-758-0. [pdf gzip'd (64KB)].
F. Xia, I.G. Clark. "Algorithms for Signal and Message asynchronous communication mechanisms and their analysis", ICACSD 2001 (Second International Conference on Application of Concurrency to System Design), Newcastle upon Tyne, UK, 25-29 June, 2001. pp 65-74. IEEE Computer Society Press, ISBN 0-7695-1071-X. [postscript gzip'd (69KB)].
A. Yakovlev, F. Xia, I. Clark. "Hets: towards harmonising time and power in systems on chip", First ACiD-WG Workshop of the European Commission's Fifth Framework Programme, Neuchatel, Switzerland, 12-13 February, 2001.
I.G. Clark, F. Xia, A. Yakovlev. "Modelling and analysis of asynchronous communication mechanisms", First ACiD-WG Workshop of the European Commission's Fifth Framework Programme, Neuchatel, Switzerland, 12-13 February, 2001.
I.G. Clark, A.C. Davies. "A comparison of some wait-free communications mechanisms", Proc. AINT'2000 (Asynchronous Interfaces: Tools, Techniques and Implementations), 19 & 20th July 2000, TU Delft, The Netherlands. [postscript gzip'd (48KB)].
I.G. Clark. "A unified approach to the study of asynchronous communication mechanisms in real time systems", Ph.D. Thesis, London University, King's College, May 2000. [postscript gzip'd (744KB)].
F. Xia, I. Clark. "Complementing role models with Petri nets in studying asynchronous data communications", pp33-50, Hardware design and Petri nets, Kluwer Academic Publishers, ISBN 0-7923-7791-5. March 2000. [postscript (94KB)].
F. Xia, A. Yakovlev, I. G. Clark. "Testing the data freshness properties of asynchronous communication mechanisms", 7th UK Asynchronous Forum, 20-21st December 1999, University of Newcastle upon Tyne. [postscript gzip'd (37KB)].
F. Xia, I. G. Clark. "Studying the three-slot asynchronous communication mechanism", 7th UK Asynchronous Forum, 20-21st December 1999, University of Newcastle upon Tyne. [postscript gzip'd (28KB)].
I. G. Clark. "Memory Optimisation for Multi-Process State Spaces", Technical Report No. CS-TR-689, Department of Computing Science, University of Newcastle upon Tyne, Newcastle, UK. December 1999. [postscript gzip'd (58KB)].
Fei Xia, Ian Clark. "Complementing the role model method with Petri Net techniques in studying issues of data freshness of the four-slot mechanism", Technical Report No. TR654, Department of Computing Science, University of Newcastle upon Tyne, Newcastle, UK. October 1998. [postscript gzip'd (52KB)].
Fei Xia, Ian Clark. "Complementing role models with Petri nets in studying asynchronous data communications", Workshop on Hardware Design and Petri Nets (HWPN'98), pp. 66--85, 19th International Conference on Applications and Theory of Petri nets. Hotel Costa da Caparica, Lisbon, Portugal, 23rd June 1998. [postscript gzip'd (99KB)].
I.G.Clark, F.Xia, A.V.Yakovlev, A.C.Davies. "Petri net models of latch metastability", IEE Electronics Letters, Vol. 34, No. 7, pp. 635--636, April 1998. (Electronics Letters Online Number 19980502).
F.Xia, I.G.Clark, A.V.Yakovlev, A.C.Davies. "Petri net models of metastable operations in latch circuits" (Full paper), Technical Report No. TR627, Department of Computing Science, University of Newcastle upon Tyne, Newcastle, UK. January 1998. [postscript gzip'd (57KB)].
A.J.Magrath, I.G.Clark, M.B.Sandler. "Design and Implementation of a FPGA Sigma-Delta Power DAC" in Signal Processing Systems: Design and Implementation, ed. M. Ibrahim, IEEE Press, ISBN 0-7803-3806-5, pp 511-521, 1998.
F.Xia, I.G.Clark, A.V.Yakovlev, A.C.Davies. "Petri net models of metastable operations in latch circuits" 3rd UK Asynchronous forum, 15-16 December 1997, Edinburgh University. [postscript gzip'd (32KB)].
A.J.Magrath, I.G.Clark, M.B.Sandler. "Design and Implementation of a FPGA Sigma-Delta Power DAC" Paper 13, IEEE Workshop on Signal Processing Systems: Design and Implementation, 3-5th November 1997, De Montfort University, Leicester, UK.
A.J.Magrath, I.G.Clark, M.B.Sandler. "A Sigma-Delta Digital Audio Power Amplifier - Design and FPGA Implementation" 103rd AES New York October 1997. Preprint number 4603(N-8). [postscript gzip'd (99KB)].
Fei Xia, Ian G.Clark, Anthony C.Davies. "Petri net based investigation of synchronisation-free interprocess communication in shared-memory real-time systems" 2nd UK Asynchronous forum, 1-2 July 1997, Newcastle University. [postscript gzip'd (67KB)].
F.Xia, I.G.Clark. "Petri net models of a class of asynchronous communication mechanisms" Research report 116/SCS/95, ISBN-1-898-783-07-1. Dept. Of Electronic and Electrical Engineering, Kings College London, 1995. [postscript gzip'd (209KB)].
I.G.Clark, R.E.Hiorns, A.C.Davies. "VHDL Implementations of integer noise shapers with floating point accuracy" 94th AES Berlin 16-19 March 1993. Preprint number 3568(D4-7).
Activities
Invited Talks, Tutorials & Seminars
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
F. Xia, I. Clark, A. Yakovlev, "Asynchronous Data Communication Mechanisms", half day tutorial, REASON (Research and Training Action for Systems on Chip Design) Tutorial Day on Systems on Chip Design, DSD'2004: The EuroMicro Symposium on Digital System Design, Rennes, France, 31st August 2004. [PowerPoint (1882KB)].
Dr. Ian G. Clark. "Asynchronous Communication Mechanisms for Heterogeneously Timed Processes". Seminar, Department of Computer Science, Adelaide University, Australia. 6th March 2003. [PowerPoint (912KB)].
Dr. Ian G. Clark. "Data Communication Mechanisms for Systems with Heterogeneous Timing". Invited talk & paper at the 2003 Heterogeneous Computer Systems Workshop, University of South Australia, Adelaide. 27th February 2003. [PowerPoint (536KB)].
Dr. I.G. Clark. "Asynchronous / Wait-Free Communication." 1st December 2000, Seminar, Department of Engineering, King's College, University of Aberdeen, UK.
Research Grant Proposals, Reports & Assessments
A.V. Yakovlev, A.M. Koelmans, F. Xia, E.G. Chester, D.J. Kinniment, A.C. Davies, S.A. Velastin, I.G. Clark "COHERENT - COmputational HEteRogEneously timed NeTworks", October 2000, EPSRC Joint Case for Support between Newcastle University and King's College London / Kingston University. (Project COHERENT granted May 2001).
A.V. Yakovlev, A.M. Koelmans, F. Xia, E.G. Chester, D.J. Kinniment, A.C. Davies, S.A. Velastin, I.G. Clark, D.A. Fraser. "EPSRC Grant Joint Final Report - Computational Heterogeneously Timed Networks (COHERENT)". February 2005. [pdf (288KB)].
A.V. Yakovlev, A.M. Koelmans, D.J. Kinniment, A.C. Davies, S.A. Velastin (not listed as author due to EPSRC rules at the time), "COMFORT - asynchronous COmmunication Mechanisms FOr Real-Time systems", August 1997, EPSRC Joint Case for Support between Newcastle University and King's College London. (Project COMFORT granted February 1998).
A.C. Davies, S.A. Velastin, D.A. Fraser, I.G. Clark, A.V. Yakovlev, D.J. Kinniment, A.M. Koelmans, F. Xia. "EPSRC Grant Joint Final Report - asynchronous COmmunication Mechanisms FOr Real-Time systems (COMFORT)". October 2001. [pdf (68KB)].
EPSRC Review & Assessment of COMFORT, June 2002 Criterion Final Assessment Research Quality Internationally leading Research Planning and Practice Tending to internationally leading Potential Scientific Impact Tending to internationally leading Output of Research Staff Tending to outstanding Communication of Research Outputs Outstanding Potential Benefits to Society Tending to outstanding Cost Effectiveness Outstanding Overall Assessment Outstanding ('Internationally leading' & 'Outstanding' are the highest ratings in their respective categories)
| EPSRC Review & Assessment of COHERENT, August 2005 | |
|---|---|
| Criterion | Final Assessment |
| Research Quality | Internationally leading |
| Research Planning and Practice | Tending to internationally leading |
| Potential Scientific Impact | Tending to internationally leading |
| Output of Research Staff | Tending to outstanding |
| Communication of Research Outputs | Outstanding |
| Potential Benefits to Society | Tending to outstanding |
| Cost Effectiveness | Tending to outstanding |
| Overall Assessment | Tending to outstanding |
Other Activities
- Programme Committee for the First Chilean Workshop on Formal Methods (ChWFM 2008), Punta Arenas, Chile, 10-15 November 2008.
