Metastability Bibliography

https://IanGClark.net/metastability.html

First Authors Surname:

A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

The Metastability bibliography contains references to papers, articles, technical reports and books on metastability and metastable states of digital hardware.

If you know of any references which should be included, or if you know a reference is available online, or have problems/comments/suggestions etc. then please email me.

This originally started out in BibTeX format. The last, now out of date file is here. Metastability Bibliography in BibTeX.

Some links.

FPGA-FAQ 0017 - Tell me about metastables - by Philip Freidin.
Metastability articles by Dr. Howard Johnson of Signal Consulting Inc.
Logic Metastability
Metastability Lecture by Dr. Charles E. Molnar
Metastability Performance of clocked FIFOs - Metastability Response in 5-V Logic Circuits
Metastability in electronics (Wikipedia)
The 'Asynchronous' Bibliography - By Ad Peeters
IEEE Spectrum on Intel Makes a Digital Coin Tosser for Future Processor - using Metastability.
IEEE Spectrum on Behind Intel's New Random-Number Generator - Metastability is referred to as an 'indeterminate state'. Published title is 'Digital Randomness'.

Acknowledgements: Thanks to Roy Bavister, Tony Davies, David Kinniment and Hugo Simpson for some of the references listed.

A
- A.M. Abas, A. Bystrov, D.J. Kinniment, O.V. Maevsky, G. Russell, A.V. Yakovlev,
  "Time Difference Amplifier".
  IEE Electronics Letters, Volume 38, No. 23, pp 1437-1438, 7th Nov 2002.
  [Abstract: Accurate measurement of edge time differences down to 10ps or less is required for tests of timing in digital systems. We describe a circuit aimed at reliably amplifying these time differences by a factor between 3 and 10 before measurement to enable greater accuracy.]
  http://www.async.org.uk/David.Kinniment/Research/papers/ElectLett2002.PDF
- Abu Hamid Ibn Muhammad Ibn Muhammad al-Tusi al-Shafi'i al-Ghazali,
  "no title".
  ~1100.
  ("Suppose two similar dates in front of a man who has a strong desire for them, but who is unable to take them both. Surely he will take one of them through a quality in him, the nature of which is to differentiate between two similar things" - he felt that this demonstrated free will).
- A.J. Acosta, M.J. Bellido, M. Valencia, A. Barriga and J.L. Huertas,
  "A CMOS metastable robust asynchronous modular arbiter",
  Proceedings of the ACiD-WG Workshop, Groningen, The Netherlands, September 9-10, 1996.
- M. Afghahi and C. Svensson,
  "Performance of synchronous and asynchronous schemes for VLSI systems",
  IEEE Transactions on Computers, Vol. 41, No. 7, pp. 858-872, 1992.
- A. Albicki and T.A. Jackson,
  "Simulation of NMOS flip-flops under asynchronous inputs",
  Proc. IEEE Custom Integrated Circuits Conf., pp. 239-244, May, 1983.
- "AMD Bus Interface Products",
  1991,
  [notes: Metastable hardened registers, Am29821/823/825. page 5.16]
- Application Note 216,
  "Arbitration in shared resource systems",
  Philips Semiconductors, AN216, 18th July, 1988,
  Online PDF
- Application Note 219,
  "A Metastability Primer",
  Philips Semiconductors, AN219, October, 1993,
  Online PDF - 15th Nov. 1989 version.
- Application Note 220,
  "Synchronizing and clock driving solutions - using the 74F50XXX family",
  Philips Semiconductors, AN220, 1st September, 1989,
  Online PDF
- J.H. Anderson and M.G. Gouda,
  "A new explanation of the glitch phenomenon",
  ACTA Informatica, Vol. 28, No. 4, pp. 297-309, 1991.
B
- M.S. Baghini, M.P. Desai,
  "Impact of technology scaling on metastability performance of CMOS synchronizing latches",
  Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, Los Alamitos, CA. IEEE Comput. Soc., pp.317-22,2002.
  [Abstract: In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are tau /sub m/ and T/sub w/. tau /sub m/ is the exponential time constant of the rate of decay of metastability and T/sub w/ is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that tau /sub m/ scales better than the technology scale factor. T/sub w/ also scales down but its factor cannot be estimated as well as that of tau /sub m/. This is because T/sub w/ is a complex function of signal and clock edge rate and logic threshold level.]
- H.T. Bahbouh, A.H. Khalil, A.E. Salama,
  "Novel design of priority arbiter",
  Proceedings of the Sixteenth National Radio Science Conference. NRSC'99, Ain Shams Univ., Cairo, Egypt, pp. C13/1-4, February, 1999.
  [Abstract: Many digital circuits with asynchronous inputs are susceptible to failure even when all their components are fault-free. They may fail as a result of metastable operation when their inputs have critical timing combinations. This paper addresses a novel priority arbiter architecture to solve the metastability problem. SPICE simulation is used to verify its performance and correctness. In contrast to other arbiters, the results showed that this new design has better immunity against metastable operation.]
- A.V. Balakrishnan,
  "Applied Functional Analysis",
  Springer Verlag, 1976.
- J.C. Barros and B.W. Johnson,
  "Equivalence of the arbiter, the synchronizer, the latch, and the inertial delay",
  IEEE Transactions on Computers, Vol. 32, No. 7, pp. 603-614, 1983.
- J. Beaston and R.S. Tetrick,
  "Designers confront metastability in boards and buses",
  Computer Design, Vol. 25, pp. 67-71, March, 1986.
- M. Bebbington,
  "Bistability and metastability in a stochastic system with positive feedback",
  30th Annual Conference Operational Research Society of New Zealand, pub. Wellington; ORNSZ; NZSA, pp. 354-359, August, 1994.
- J.M. Bellido, A.J. Acosta, J. Luque, A. Barriga and M. Valencia,
  "Evaluation of metastability transfer models - an application to an N-bistable CMOS synchronizer",
  International Journal of Electronics, Vol. 79, No. 5, pp. 585-593, 1995.
- C.H. van Berkel and C.E. Molnar,
  "Beware the Three-Way Arbiter",
  IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 840-848, June 1999.
- R.G. Bertle,
  "The elements of Real Analysis",
  John Wiley and Sons, New York", 2nd Ed., 1976.
- N.P. Bhatia and G.P. Szego,
  "Stability Theory of Dynamical Systems",
  Springer Verlag, 1970.
- W.R. Blood Jnr.,
  "MECL System Design Handbook",
  Motorola Semiconductor Products Inc. 3rd Ed., 2nd printing Phoenix, 1982.
  [notes: Compiled by Motorola Applications Engineering Dept.]
- T. Bowns,
  "Control metastability in high speed CMOS circuits",
  Electronic Design, Vol. 39, p74, 26th September, 1991.
- R. Breuninger, M. Higgs and R. Schwartz,
  "Advanced CMOS Logic Designers Handbook",
  Texas Instruments, 1987.
  [notes: pages 3.1-3.12, 3.29-3.36]
- C. Brown and K. Feher,
  "Measuring metastability and its effect on communication signal processing systems",
  IEEE Transactions on Instrumentation and Measurement, Vol. 46, No. 1, p61, 1997.
- D. Bursky,
  "Clock Free Macrocells Simplify Asynchronous design",
  Electronic Design, Vol. 36, pp. 53-56, July, 1988.
- R.E. Bryant and C.J.H. Seger,
  "Formal verification of digital circuits using symbolic ternary system models",
  Lecture Notes in Computer Science, Vol. 531, pp. 33-43, 1991.
- J.A. Brzozowski and M. Yoeli,
  "On a Ternary Model of Gate Networks",
  IEEE Transactions on Computers, Vol. C-28, No. 3, pp. 178-184, March, 1979.
- J.A. Brzozowski and C.J. Seger,
  "Correspondence between ternary simulation and binary race analysis in gate networks",
  Lecture Notes in Computer Science, Vol. 226, pp. 69-78, 1986.
- J.A. Brzozowski and C.J. Seger,
  "A Characterization of Ternary Simulation of Gate Networks",
  IEEE Transactions on Computers, Vol. C-36, No. 11, pp. 1318-1327, November, 1987.
- J.A. Brzozowski and C.J.H. Seger,
  "Advances in Asynchronous Circuit Theory; Part I: Gate and Unbounded Inertial Delay Models",
  Bull. EATCS, No. 42, pp. 198-249, October, 1990.
- J.A. Brzozowski and C.J.H. Seger,
  "Asynchronous Circuits",
  Springer Verlag, 1995.
  [notes: Section on Multiple Winner Models which allow modelling of Metastable oscillations.]
- J. A. Brzozowski,
  "Delay-Insensitivity and Ternary Simulation",
  Proc. of the First International Conference on Semigroups and Algebraic Engineering, pub. World Scientific Publishing Co. Pte. Ltd., Singapore, March, 1997.
- J. Buridan (Rector of Paris University),
  "no title".
  ~1340.
  (Buridan's Ass (A dog with two bowls), "Should two courses be judged equal, then the will cannot break the deadlock, all it can do is to suspend judgement until the circumstances change, and the right course of action is clear.")
- A. Bystrov and A. Yakovlev,
  "Ordered arbiters",
  IEE Electronics Letters, Vol. 35, No. 11, pp. 877-879, 27th May, 1999.
  [Abstract: The granting of requests in the order of their arrival is not satisfied in existing l/n arbiters, such as token rings, tree arbiters and networks of two-way arbiters. The proposed solution stores pending grants in a FIFO, thus maximally preserving the request order, improves fairness and offers lower metastability rate.]
C
- A. Cantoni, J. Walker, T.D., Tomlin,
  "Characterization of a Flip-Flop Metastability Measurement Method",
  IEEE Trans. on Circuits and Systems, Part 1 regular papers Vol. 54, No. 5, pp. 1032-1040, 2007.
- J. Calvo, M. Valencia and J.L. Huertas,
  "Metastable operation in RS Flip Flops",
  International Journal of Electronics, Vol. 70, No. 6, pp. 1073-1091, 1991.
- I. Catt,
  "Time Loss through gating of asynchronous logic signal pulses",
  IEEE Trans. on Electronic Computers, Vol. EC-15, pp. 108-111, February, 1966.
- T.J. Chaney, W.M. Littlefield,
  "The glitch phenomenon",
  Computer System Lab, Washington University, St Louis, MO, Tech. Memo. 10, December 1966.
- T.J. Chaney, S.M. Ornstein and W.M. Littlefield,
  "Beware the Synchronizer",
  Proc. IEEE Compcon., pp. 317-319, September, 1972.
- T.J. Chaney and C.E. Molnar,
  "Anomalous Behavior of Synchronizer and Arbiter Circuits",
  IEEE Transactions on Computers, Vol. C-22, No. 4, pp. 421-422, April, 1973.
- T.J. Chaney and F.U. Rosenberger,
  "Characterisation and scaling of MOS flip-flip performance in synchroniser applications",
  Proc. Caltech Conf. VLSI, pp. 357-374, January, 1979.
- T.J. Chaney, "Comments on 'A Note on Synchronizer and Interlock Maloperation'",
  IEEE Transactions on Computers, Vol. C-28, pp. 802-804, October, 1979.
- T.J. Chaney, "Circuit design for",
  IEEE Journal of Solid State Circuits, Vol. SC-17, August, 1982.
- T.J. Chaney,
  "Measured Flip-Flop Responses to Marginal Triggering",
  IEEE Transactions on Computers, Vol. C-32, No. 12, pp. 1207-1209, December, 1983.
- T.J. Chaney,
  "Flip-flop flaw",
  EDN, Vol. 28, No. 4, p23, 1983.
  [notes: letter.]
- T.J. Chaney,
  "A Comprehensive Bibliography on Synchronizers and Arbiters",
  Institute of Biomedical Computing, Washington Uni., St Louis, October, 1985.
- T.J. Chaney,
  "My Work on All Things Metastable OR: (Me and My Glitch)",
  Blendics White Paper, March 2012.
  http://blendics.com/wp-content/uploads/2016/08/My-Work-on-All-Things-Metastable-OR-Me-and-My-Glitch.pdf
  Also at: http://www.arl.wustl.edu/~jst/cse/260/glitchChaney.pdf
- D.M. Chapiro,
  "Globally asynchronous locally synchronous systems",
  PhD Thesis, Stanford University, STAN-CS-84-1026, October, 1984.
- D.M. Chapiro,
  "Reliable high speed arbitrary and synchronization",
  IEEE Transactions on Computers, Vol. C-36, pp. 1251-1255, October, 1987.
- A. Chattopadhyay, Z. Zilic,
  "High speed asynchronous structures for inter-clock domain communication",
  ICECS 2002. 9th IEEE International Conference on Electronics, Circuits and Systems. IEEE. Vol.2, pp.517-520, September, 2002.
  [Abstract: This paper describes a globally asynchronous, locally dynamic system (GALDS) design paradigm. In a GALDS design, many synchronous blocks are inter-connected using dedicated asynchronous links. Each synchronous block is associated with a local clock generator and features dynamic frequency scaling in order to utilize the least possible power for the required performance to be achieved. Two different asynchronous structures are explored in this paper and they each feature high throughput, modular design and high tolerance to metastability errors that occur when communicating between clock domains. These structures utilize a 4-phase dual track asynchronous control circuit to control either a single direction FIFO with data traveling uniquely in one direction or a bidirectional FIFO that is capable of transmitting data simultaneously in both directions by precisely controlling when data has access to a common, shared datapath. These structures have been created in TSMC's CMOSP18 technology.]
- A.N. Chebotarev,
  "Hazards in asynchronous logic circuits",
  Kibernetika, No. 4, pp. 8-1?, 1976.
- H.B. Chenoweth,
  "Soft failures and reliability",
  Proceedings Annual Reliability and Maintainability Symposium, pp. 419-424, 1990.
- J.A. Cherry and W.M. Snelgrove,
  "Clock jitter and quantizer metastability in continuous-time delta-sigma modulators",
  IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, Vol. 46, No. 6, pp. 661-676, June, 1999.
  [Abstract: The performance of continuous-time (CT) delta-sigma modulators ( Delta Sigma M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT Delta Sigma M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT Delta Sigma M given jitter and metastability constraints.]
- J. Chiang and D. Radhakrishnan,
  "Hazard-free Design of Mixed Operating Mode Asynchronous Sequential Circuits",
  Int. Journal Electronics, Vol. 68, No. 1, pp. 23-37, 1990.
- G. Chiorboli, B. De Salvo, G. Franco, C. Morandi,
  "Some thoughts on the word error rate measurement of A/D converters",
  1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology. IEEE. Vol. 3, pp. 453-456, September, 1998.
  [Abstract: The word error rate (WER) of an A/D converter quantifies the probability that a wrong output code occurs because of metastability, intrinsic noise or aperture uncertainty. It can be measured in real-time, as it is customary for very low WER converters, or by post processing, when the WER is more relevant. In the paper the possible causes of inaccuracy are analyzed. First, the existing methods are reviewed, then the errors which may arise from the conventional analysis of experimental data are discussed, and it is shown that these errors can be removed in the case of post processing. Finally, the requirements on the test bench noise are discussed in connection with the qualified error level (i.e. 1, 2, 4, .., 16 LSB) and with the expected error rate.]
- T. Chu,
  "Automatic synthesis and verification of hazard-free control circuits from asynchronous finite state machine Specifications",
  Proc. International Conf. Computer Design (ICCD), IEEE Computer Society Press, pp. 407-413, October, 1992.
- T. Chu,
  "On the specification and synthesis of hazard-free asynchronous control circuits",
  Proc. International Symposium on Circuits and Systems, IEEE Computer Society Press, Vol. 3, pp. 1495-1498, 1993.
- T. Chu,
  "Synthesis of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications",
  Journal of VLSI Signal Processing, Vol. 7, No. 1/2, pp. 61-84, February, 1994.
- E.C.Y. Chung and L. Kleeman,
  "Metastable-robust Self-timed Circuit Synthesis from Live Safe Simple Signal Transition Graphs",
  Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, pp. 97-105, November, 1994.
- I.G. Clark, F. Xia, A.V. Yakovlev and A.C. Davies,
  "Petri net models of latch metastability",
  IEE Electronics Letters, Vol. 34, No. 7, pp. 635-636, April, 1998.
  [notes: IEE online number 19980502]
- P. Corsini,
  "Self-synchronizing Asynchronous Arbiter",
  Digital Processes, Vol. 1, pp. 67-73, 1975.
- P. Corsini,
  "Speed Independent Asynchronous Arbiter",
  IEE Proceedings, Part E, Computers and Digital Techniques, Vol. 2, pp. 221-222, October, 1979.
- J. Cortadella, L. Lavagno, P. Vanbekbergen and A. Yakovlev,
  "Designing Asynchronous Circuits from Behavioural Specifications with Internal Conflicts",
  Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, pp. 106-115, November, 1994.
- J. Cortadella, L. Lavagno, P. Vanbekbergen and A. Yakovlev,
  "Designing Asynchronous Circuits from Behavioural Specifications with Internal Conflicts",
  Technical Report UPC/DAC No. 94/08, Universitat Politecnica de Catalunya, 1994.
- E.R. Cortes-Ramos,
  "Metastability and the synchronization failure: a theoretical and experimental analysis",
  PhD Thesis, Tufts University, Dept. of Electrical Engineering, 1986.
  [notes: 150 pages]
- G.R. Couranz,
  "An analysis of binary circuits under marginal triggering conditions",
  Computer Systems Laboratory Technical Report 15, Washington University, St Louis, Mo, November, 1969.
- G.R. Couranz and D.F. Wann,
  "Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region",
  IEEE Transactions on Computers, Vol. C-24, No. 6, pp. 604-616, June, 1975.
- J. Cox and G.L. Engel,
  "Metastability and Fatal System Errors",
  Blendics LLC, 5th November 2010.
  A white paper on metastability in synchronizers was submitted by Blendics staff to the National Research Council of the National Academies of Science for their project, "Electronic Vehicle Controls and Unintended Acceleration," associated with an on-going study of future automotive safety requirements.
  http://www.blendics.com/images/Resource_Library/metastability%20and%20fatal%20systems%20errors.pdf
- J. Cox, T. Chaney and D. Zar,
  "Simulating the Behavior of Synchronizers",
  Blendics LLC Whitepaper, 13th February 2011.
  http://www.blendics.com/images/Resource_Library/simulating%20the%20behavior%20of%20synchronizers.pdf
- A. Cunningham,
  "A study and characterisation of metastability in AT∓T's ORCA FPGAs",
  Masters Thesis, Lehigh University, 1995.
  [notes: 108 pages]
D
- A.C. Davies,
  "Analysis of the Metastable Dynamics of Bistable Flip-Flops",
  6th Int. Symp. on Networks, Systems and Signal Processing, pp. 379-382, June, 1989.
- A.C. Davies,
  "Modelling and Simulation of the Metastability of Flip-Flops",
  4th Tagung Schaltkreisentwarf, Technishe Universitat Dresden, February, 1990.
- A.C. Davies,
  "Asynchronous Communications Between Locally Synchronous Subsystems",
  Proc. Polish - Czech - Hungarian Workshop on Circuit Theory, Signal Processing and Applications, pp. 75-80, September, 1997.
- A.C. Davies,
  "Metastability in Latches, Arbiters and Data-Convertors",
  IEEE International Symposium on Signals, Circuits and Systems SCS'99, pp. 1-4 (Invited Paper), 6th-7th July, 1999.
  [Abstract: Real-time digital systems and asynchronous computer systems have an inherent risk of occasional failures due to metastability in various components used to control data-transfers. This possibility has been known for a long time, although it is sometimes forgotten or overlooked. There is renewed interest in asynchronous computer systems because of the prospects they offer for lower power operation and improved electromagnetic compatibility compared to conventional fully synchronous systems. As a result, design approaches to minimise metastability effects need to be adopted. Recent increased understanding of nonlinear dynamics and the availability of software for the accurate simulation and visualisation of dynamic behaviour enables metastability to be investigated and demonstrated much more readily. This paper provides a mainly-tutorial review of how metastability arises in various commonly-used components, illustrated with the results of simulations.]
- A.C. Davies,
  "Multi-Flops - A View of the Dynamical Behaviour",
  7th International Specialist Workshop on NonLinear Dynaics of Electronic Subsystems (NDES'99), Ronne, Island of Bornholm, Denmark, pp. 133-136, 15th-17th July, 1999.
- C. Dike and E. Burton,
  "Miller and noise effects in a synchronizing flip-flop",
  IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 849-855, June, 1999.
  [Abstract: The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and tau . The flip-flop was fabricated on a 0.25- mu m CMOS process.]
- Dillenger,
  "VLSI Engineering",
  Prentice-Hall, ISBN 013-942731-7-025, 1988.
- S. Dingman,
  "Determine PLD metastability to derive ample MTBFs",
  EDN, Vol. 36, No. 16, pp. 147-154, 5th August, 1991.
- D.C. Doughty, S. Lemon and P. Bonneau,
  "Asynchronous inputs and flip-flop metastability in the CLAS trigger at CEBAF",
  "Nuclear Science Symposium and Medical Imaging Conference, IEEE Transactions on Nuclear Science 1993, Vol 40, pp. 680-684, 1992.
- H.F. Dudziak,
  "The behavior of flip-flops under different boundary conditions",
  Microelectronics Journal, Vol. 26, No. 4, pp. 361-374, 1995.
- R.W. Dutton,
  "Metastability of CMOS latch flip-flops - reply",
  IEEE Journal of Solid-State Circuits, Vol. 27, No. 1, pp. 131-132, 1992.
E
- J.E. Eklund and C. Svensson,
  "Metastability determines the noise in fast and accurate A/D converters",
  International Workshop on ADC modeling and testing, Eds. J. Halttunen, P. Daponte, L. Michaeli, "ADC Modeling and Testing", Pub. Finnish Society of Automation, Helsinki, pp. 171-176, June, 1997.
- J. Eklund, C. Svensson,
  "Influence of metastability errors on SNR in successive-approximation A/D converters",
  Analog Integrated Circuits & Signal Processing, Pub. Kluwer Academic Publishers, Vol. 26, No. 3, pp. 191-198, March, 2001.
  [Abstract: We present a theory for metastability error power in successive approximation A/D converters. The traditional measure, BER, does not account for the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and a signal-to-metastability-error-ratio, SMR, is suggested as a new measure, suppressing SMR below SNR imposes a gain requirement on the comparator.]
- A. Elamawy, M. Naraghipour and M. Hegde,
  "Noise modelling effects in redundant synchronisers",
  IEEE Transactions on Computers, Vol. 42, No. 12, pp. 1487-1494, 1993.
- G. Elineau and W. Wisebeck,
  "A New J-K Flip-Flop for Synchronizers",
  IEEE Transactions on Computers, Vol. C-26, pp. 1277-1278, December, 1977.
F
- S.T. Flannagan,
  "Synchronization Reliability in CMOS Technology",
  IEEE Journal of Solid-State Circuits, Vol. SC-20, pp. 880-882, August, 1985.
- W. Fleischhammer and O. Dortok,
  "The anomalous behavior of flip-flops in synchronizer circuits",
  IEEE Transactions on Computers, Vol. C-28, No. 3, pp. 273-276, March, 1979.
  [notes: see Lacroix 1982]
- C. Foley,
  "Characterizing metastability",
  2nd International Symposium on Advanced Research into Asynchronous Circuits and Systems, IEEE Computer Society Press, pp. 175-187, March, 1996.
- G.G. Freeman, D.L. Liu, B. Wooley and E.J. McCluskey,
  "Two CMOS Metastable Sensors",
  Proc. International Test Conference, Centre for Reliable Computing, Stanford University, 1986.
  [notes: Paper 4.1 IEEE CH2339-0/86/0000/014]
- E.G. Friedman,
  "The Limiting performance of a CMOS bistable register based on wave form considerations",
  International Journal of Electronics, Vol. 73, No. 2, pp. 371-384, 1992.
- E.G. Friedman,
  "Latching characteristics of a CMOS Bistable register",
  IEEE Transactions on Circuits and Systems I-Fundamental Theory and Applications, Vol. 40, No. 12, pp. 902-908, 1993.
- G. Frosini and G. B. Gerace,
  "Synthesis of asynchronous sequential circuits with master-slave subcircuits",
  Annual Symposium on Switching and Automata Theory, IEEE Computer Society Press, pp. 60-78, 1971.
G
- T.J. Gabara, G.J. Cyr and C.E. Stroud,
  "Metastability of CMOS master slave flip-flops",
  IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, Vol. 39, No. 10, pp. 734-740, 1992.
- A. Galves, E. Olivieri and M.E. Vares,
  "Metastability for a class of dynamical systems subject to small random perturbations",
  Annals of Probability, Vol. 15, No. 4, pp. 1288-1305, 1987.
- R. Ginosar,
  "Fourteen Ways to Fool Your Synchronizer",
  Proceedings Ninth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003). IEEE Comput. Soc., May, 2003.
  [notes: PowerPoint]
- R. Ginosar,
  "Metastability and Synchronizers: A Tutorial",
  IEEE Design and Test of Computers, Vol. 28, No. 5, pp. 23-25, 2011.
- L.A. Glasser and D.W. Dobber-Puhl,
  "The Design and Analysis of VLSI Circuits",
  Addison-Wesley, ISBN 0-201-12580-3, 1985.
  [notes: Section 6.5]
- M.R. Greenstreet and P. Cahoon,
  "How fast will the flip flop?"
  Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, pp. 77-86, November 1994.
- D. Grosse,
  "Keep metastability from killing your digital design",
  EDN, Vol. 39, p109, 23rd June, 1994.
H
- C.A. Halijak,
  "Characteristic equation and stable states of flip-flops",
  Comp. Elect. Eng., Vol. 3, pp. 339-343, 1976.
- J.W. Haus,
  "Metastability in continuum systems",
  PhD Thesis, Catholic University of America, 1974.
  [notes: 105 pages]
- M.S. Haydt, S. Mourad,
  "The effect of feedback characteristics on metastability in CMOS latches",
  Proceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems. MIXDES 2000. Tech. Univ. Lodz, Poland, pp.275-280, June, 2000.
  [Abstract: Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, uses of a third order model taking into account that the effect of the feedback transistors is necessary for correct modeling of metastability. A new simulator was developed for this study. The results presented here show that when modeling a CMOS latch for metastability purposes, it is not sufficient to use a second order circuit that neglects the effect of the feedback transistor. The simulator can also be used to study the effect of power supply noise and applied to interconnect models to study crosstalk.]
- M.S. Haydt, S. Mourad,
  "Special simulator to study metastability [CMOS latch]",
  SPIE-Int. Soc. Opt. Eng. Proceedings of Spie - the International Society for Optical Engineering, Vol. 4182, pp. 178-186, September, 2000.
  [Abstract: Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, use of a third order model, taking into account that the effect of the feedback transistor is necessary for correct modeling of metastability. A new simulator was developed for this study. The results presented here show that when modeling a CMOS latch for metastability purposes, it is not sufficient to use a second order circuit that neglects the effect of the feedback transistor. While second order models are helpful in understanding how to model the circuit in the region, they do not provide sufficient information to accurately predict the essential parameter tau the maximum time at which the circuit may leave the metastable state. The only way to analyze such a circuit is to simulate it, using a simulator that combines small signal and large signal analysis. Future work on metastability will include modeling the feedback transistor as a resistor, and determining whether such a model is a reasonable simplification. The simulator can be modified easily to model small transistor geometry devices and to study the effect of large signal noise, such as ground and power supply bounce, on metastability. The model may also be applied to an interconnect model to improve delay and crosstalk simulations.]
- M.S. Haydt, S. Mourad, W. Terry, J. Terry,
  "A new model for metastability",
  ICECS 2002. 9th IEEE International Conference on Electronics, Circuits and Systems, IEEE. Vol.1, pp. 413-616, September, 2002.
  [Abstract: Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, uses of a third order model taking into account that the effect of the feedback transistors is necessary for correct modeling of metastability. A new simulator was developed for this study. The results presented here show that when modeling a CMOS latch for metastability purposes, it is not sufficient to use a second order circuit that neglects the effect of the feedback transistor. The simulator can also be used to study the effect of power supply noise and applied to interconnect models to study crosstalk.]
- F.J. Hill and G.R. Peterson,
  "Computer aided logic design with emphasis on VLSI",
  Wiley, 4th Edition, pp. 445-448, 1993.
  [notes: 14.9 Eliminate the fundamental-mode restriction at your own risk]
- J.H. Hohl, W.R. Larsen and L.C. Schooley,
  "Prediction of error probabilities for integrated digital synchronizers",
  IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 236-244, April, 1984.
- P. Horowitz and W. Hill,
  "The Art of Electronics",
  Cambridge University Press, 2nd Edition, 1994.
  [notes: pages 511, 552, 757. Chapters 8, 11.]
- J. Horstmann and R. Coates,
  "Metastable behaviour of LSI Logic flip-flops, 1.5u technology",
  Technical Report, LSI Logic Corp., Palo Alto, CA, September, 1987.
- J.U. Horstmann, H.W. Eichel and R.L. Coates,
  "Metastability behavior of CMOS ASIC Flip-Flops in Theory and Test",
  IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp. 146-157, February, 1989.
- M. Hurtado and D.L. Elliott,
  "Ambiguous Behavior of Logic Bistable Systems",
  Proceedings of the 13th Annual Allerton Conference on Circuit & System Theory, pp. 605-611, October, 1975.
- M. Hurtado,
  "Structure and preformance of asymptotically bistable dynamical systems",
  PhD Thesis, Sever Institute, Washington University, 1975.
- T. Husain,
  "Topology and maps",
  Plenum Press, 1977.
I
- "Metastability and incompletely possed problems",
  Springer Verlag, ISBN 0387964622, 372 pages, Vol. 3, 1987.
- A.F. Izmailov and A.S. Myerson,
  "Theory of metastable state relaxation for noncritical binary systems with nonconserved order parameter",
  Physica A, Vol. 192, No. 1-2, pp. 85-106, 1993.
J
- T.A. Jackson,
  "Metastable operation of nMOS flip-flops",
  PhD Thesis, Elec. Eng. Dept. Univ of Rochester, NY, 1985.
- T.A. Jackson and A. Albicki,
  "Reduction of the probability of synchronization failure in NMOS systems through proper flip-flop design",
  Proc. 6th Biennial University/Government/Industry Microelectronics Symp., pp. 177-182, June, 1985.
- T.A. Jackson and A. Albicki,
  "Modelling and Simulation of NMOS flip-flops in metastable region",
  Proc. 12th Int. Conf. Applied Simulation and Modelling, July, 1985.
- T.A. Jackson and A. Albicki,
  "Analysis of Metastable Operation in D Latches",
  IEEE Transactions on Circuits and Systems, Vol. 36, No. 11, pp. 1392-1404, November, 1989.
- T.A. Jackson and A. Albicki,
  "Analysis of a double latch synchroniser circuit",
  IEE Electronics Letters, Vol. 25, No. 5, pp. 315-316, 1989.
- T. Jackson,
  "FIFO Memories: Solution to reduced FIFO Metastability",
  Technical Report SCAA011A, Texas Instruments, 1996.
- R.C. Jeager and R.M. Fox,
  "Phase plane analysis of the upset characteristics of CMOS RAM cells",
  Proc. 6th Biennial University/Government/Industry Microelectronics Symp., pp. 183-187, June, 1985.
- J. JuanChico, M.J. Bellido, A.J. Acosta, M. Valencia and J.L. Huertas,
  "Analysis of metastable operation in a CMOS dynamic D-latch",
  Analog Integrated Circuits and Signal Processing, Vol. 14, No. 1-2, pp. 143-157, 1997.
- J.R. Jump and P.S. Thiagarajan,
  "On the interconnection of asynchronous control structures",
  Journal of the ACM, Vol. 22, pp. 596-612, October, 1975.
K
- T. Kacprzak,
  "Analysis of metastable operation in cross-coupled CMOS circuits",
  Proceedings of the Midwest Symposium on Circuits and Systems, pp. 190-193, August, 1985.
- T. Kacprzak, A. Albiki and T.A. Jackson,
  "Design of N-well CMOS flip-flops with minimum failure rate due to metastability",
  Proc. of IEEE ISCAS, pp. 765-767, 1986.
- T. Kacprzak and A. Albicki,
  "Analysis of Metastable Operation in RS CMOS Flip-Flops",
  IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 1, pp. 57-64, February, 1987.
- T. Kacprzak,
  "Analysis of Oscillatory Metastable Operation of an RS Flip-Flop",
  IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 260-266, February, 1988.
- J. Kalisz, Z. Jachna,
  "Metastability tests of flip-flops in programmable digital circuits",
  MICROELECTRONICS JOURNAL Vol. 37, No. 2, pp. 174-180, 2006.
- R. Katz,
  "Contemporary Logic Design",
  The Benjamin Cummings Publishing Company Inc., 1994.
  [notes: chapter 6, pp.309-313, p320.]
- L.S. Kim and R.W. Dutton,
  "Metastability of CMOS latch/flip-flop",
  IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, pp. 942-951, August, 1990.
- T.M. King,
  "Test of metastability failure rates in synchronizer circuits",
  Masters Thesis, Dept. of Electrical Engineering and Computer Science, MIT, 1990.
  [notes: 40 pages]
- D.J. Kinniment and D.B.G. Edwards,
  "Circuit technology in a large computer system",
  Presented at the joint IERE-IEE-BCS Conference on Computers - Systems and Technology, London, 1972.
  [SUMMARY: In the design of a large high-speed computer, the size of the system leads to long cable delays for data transmitted between different parts of the machine. This problem and the interconnexion of a high-speed e.c.l. circuit family are discussed, and comment is made on future lines of development for technology in high-speed computers. Priority circuits in a large asynchronous system also present difficulties not usually encountered in smaller machines and a discussion of how these difficulties arise is presented.]
  http://www.async.org.uk/David.Kinniment/Research/papers/system1972.PDF
- D.J. Kinniment and D.B.G. Edwards,
  "Circuit Technology in a Large Computer System",
  The Radio and Electronic Engineer, Vol. 43, No. 7, pp. 435-441, July, 1973.
  [notes: Based on paper presented at the joint IERE-IEE-BCS Conference on Computers-Systems and Technology, London 24 - 27 1972.]
- D.J. Kinniment and J.V. Woods,
  "Synchronisation and arbitration circuits in digital systems",
  IEE Proceedings, Vol. 123, No. 10, pp. 961-966, October, 1976.
  [Abstract: Synchronisation of two independently clocked processor units, or arbitration between two asynchronous units requesting access to a common resource, can cause serious time losses in a computer system. The ways in which these problems arise are considered, and a theoretical basis for calculation of the time losses is presented. The theory is then correlated with measurements on practical devices, and currently available methods for minimising the time loss are evaluated. Conditions necessary for prediction of the performance of synchronisers and arbiters are established and it is shown that design principles exist which allow the construction of systems with known reliability.]
  http://www.async.org.uk/David.Kinniment/Research/papers/IEE1976.pdf
- D. Kinniment, A.V. Yakovlev and B. Gao,
  "Metastable behaviour in arbiter circuits",
  Technical Report TR604, University of Newcastle upon Tyne, March, 1997.
- D. Kinniment, A.V. Yakovlev and B. Gao,
  "Metastable Behavior and System Performance",
  Proc. 2nd UK Asynchronous Forum, University of Newcastle upon Tyne, July, 1997.
- D.J. Kinniment, B. Gao, A.V. Yakovlev and F. Xia,
  "Towards asynchronous A-D conversion",
  Proc. 4th Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC'98), San Diego, CA., IEEE Computer Society Press, pp. 206-215, March/April, 1998.
  [Abstract: Analog to digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially severe. We estimate the frequency of these errors in a successive approximation converter, and compare the results with asynchronous designs using both a fully speed-independent, and a bundled data approach. It is shown that an asynchronous converter is more reliable than its synchronous counterpart, and that the bundled data design is also faster, on average, than the synchronous design. We also demonstrate trade-offs involved in asynchronous converter designs, such as speed, robustness to delay variations, circuit size and design scalability.]
- D.J. Kinniment, A.V. Yakovlev,
  "Low power, low noise micropipelined flash A-D converter",
  IEE Proceedings: Circuits, Devices & Systems, Vol. 146, No. 5, pp. 263-267, October, 1999.
  [Abstract: Metastability in the comparators of high speed synchronous flash A-D converters is a source of noise in the output. Pipelining can reduce metastability errors but can consume significant power in synchronous systems, and techniques have been described which aim to reduce the power, but can lead to nonlinearity. It is shown that power can also be reduced without loss of linearity by asynchronous micropipelining techniques which allow the comparison times to vary without a high probability of metastability noise. Other advantages resulting from asynchronous internal timing include a reduction in clock noise, and improved tolerance to process and interconnect delays.]
- D. Kinniment, A. Yakovlev, B. Gao,
  "Synchronous and asynchronous A-D conversion",
  IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, Vol. 8, No. 2, pp. 217-220, April, 2000.
  [Abstract: Analog-digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. It is shown that an asynchronous converter in which the conversion time is not bounded is faster, on average, than the synchronous design. Real-time applications require the data to be produced within a fixed time, and failures may occur with the long conversion times that can arise with fully asynchronous converters. For these applications, we show that an internally asynchronous bounded time converter is both faster and more reliable than a synchronous converter.]
- D.J. Kinniment, A. Bystrov, A.V. Yakovlev,
  "Synchronization circuit performance."
  IEEE Journal of Solid-State Circuits, Vol. 37, No. 2, pp 202-209, February 2002.
  http://www.async.org.uk/David.Kinniment/Research/papers/Jssc2002.PDF
- D.J. Kinniment, E.G. Chester,
  "Design of an on-chip random number generator using metastability."
  ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference. Univ. Bologna, Italy, pp.595-598, September, 2002.
  [Abstract: This paper shows that the internal noise in a bistable exhibits a Gaussian distribution, and is close to the value expected from thermal agitation. We describe a random number generator based on this property that is capable of on chip integration, and is a primary source of high entropy data at 100 MHz. The device is held close to metastability by a feedback loop, and is therefore relatively insensitive to circuit asymmetries and drift. Measurements of post-processed data from this source also show a relatively high bit rate and sequences of 2/sup 23/ bits are shown to pass stringent tests for randomness.]
  http://www.async.org.uk/David.Kinniment/Research/papers/ESSCIRC2002.PDFF
- D.J. Kinniment,
  "Synchronizers and Arbiters OR 1000 years of indicision"
  14th UK Asynchronous Forum, Newcastle upon Tyne, UK. 30th June and 1st July 2003.
- D.J. Kinniment and A.V. Yakovlev,
  "Low latency synchronization through speculation",
  14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings. Lecture Notes in Computer Science 3254 Springer 2004. ISBN 3540230955. pp. 278-288.
  [Abstract: Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduced significantly, typically to half the number of clock cycles required for high reliability, by speculating that a long synchronization time is not required. The small number of synchronization metastability times longer than normal are detected, and subsequent computations re-evaluated, thus maintaining the reliability of the system.]
  http://www.async.org.uk/David.Kinniment/Research/papers/speculatio.PDF
- D. Kinniment, K. Heron, G. Russell,
  "Measuring Deep Metastability",
  12th International Symposium on Asynchronous Circuits and Systems Conf. 2006 (Async 2006), Grenoble, France, March 2006. ISBN 0769524982. pp. 2-11.
  [Abstract: Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude, and events with long metastable times are selected from the large number of more normal events. The relationship found between input times and the resulting output times is dependent on accurate measurement of input time distributions with deviations of less than 10ps. We show how the distribution of D to Clock times at the input can be characterised in the presence of noise, and how predictions of failure rates for long synchronizer times can be made. Anomalies such as the increased failure rates in a master slave synchronizer produced by the back edge of the clock are measured.]
  http://www.async.org.uk/David.Kinniment/Research/papers/Async2006.pdf
- D.J. Kinniment, C.E. Dike, K. Heron, G. Russell, A.V. Yakovlev,
  "Measuring Deep Metastability and Its Effect on Synchronizer Performance",
  IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 9, pp. 1028-1039, 2007.
- D.J. Kinniment, A. Yakovlev,
  "Synchronization and Arbitration in Digital Systems",
  Wiley, December 2007, 280 pages, ISBN: 978-0-470-51082-7.
  http://eu.wiley.com/WileyCDA/WileyTitle/productCd-047051082X.html
  Buy from Amazon.co.uk
- D.J. Kinniment,
  "Metastability and Synchronisation in SOCs and NOCs",
  Async 2008 Tutorial, Newcastle upon Tyne, 7th April 2008.
  http://async.org.uk/async2008/keynote-tutorials.html#tutorial1 - Abstract and Slides.
- D.J. Kinniment,
  "He Who Hesitates is Lost: Decisions and free will in men and machines",
  eBook, School of Electrical, Electronic and Computer Engineering, Newcastle University, 2011.
  http://www.async.org.uk/David.Kinniment/
- K. Kittrell,
  "1Kx9x2 Asynchronous FIFOs SN74ACT2235 and SN74ACT2236",
  Technical Report SCAA010A, Texas Instruments, 1995.
- K. Kittrell,
  "FIFO Solutions for Increasing Clock Rates and Data Widths",
  Technical Report SZZA001A, Texas Instruments, 1996.
- L. Kleeman and A. Cantoni,
  "Can redundancy and masking improve the performance of synchronizers",
  IEEE Transactions on Computers, Vol. 35, pp. 643-646, July, 1986.
  [notes: has truth tables with 0,M,1 in. The M is for Meta!. Majority voting. Redundancy refs. when M settles truth table changes state!]
- L. Kleeman,
  "Service and Metastability Performance of Arbiters" (PDF 82MB),
  PhD Thesis, Dept. of Electrical and Computer Eng., Univ. of Newcastle, Australia, August, 1986.
  Abstract
- L. Kleeman and A. Cantoni,
  "On the Unavoidability of Metastable Behavior in Digital Systems",
  IEEE Transactions on Computers, Vol. C-36, No. 1, pp. 109-112, January, 1987.
  [notes: has regions of attraction pictures]
- L. Kleeman and A. Cantoni,
  "Metastable behavior in Digital Systems",
  IEEE Design & Test of Computers, Vol. 4, No. 6, pp. 4-19, December, 1987.
- L. Kleeman and A. Cantoni,
  "Can redundancy and masking improve the performance of synchronisers - reply",
  IEEE Transactions on Computers, Vol. 38, No. 5, p753, 1989.
- L. Kleeman,
  "The jitter model for metastability and its application to redundant synchronizers",
  IEEE Transactions on Computers, Vol. 39, No. 7, pp. 930-942, 1990.
- G. Kulkarni, V. Naware and M. Govindarajan,
  "Burst error generator using flip-flop metastability",
  IEE Electronics Letters, Vol. 35, No. 2, pp. 108-109, 21st January, 1999.
  [Abstract: A novel burst error generator for communications systems testing is presented which is based on the phenomenon of metastability observed in flip-flops. Bursts can be created with predetermined bit error ratios by means of an external control voltage. The errors appear to follow a double Poisson distribution, characteristic of the Neyman type A contagious process.]
L
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- G. Lacroix, P. Marchegay and N. Hossri,
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  IEEE Transactions on Computers, Vol. 31, No. 1, pp. 77-78, January, 1982.
  [notes: See Fleischhammer 1979]
- L. Lamport,
  "Buridan's Principle",
  Digital Equipment Corporation, Systems Research Center, 31 October 1984, revised: 21 January 1986.
  http://research.microsoft.com/users/lamport/pubs/buridan.pdf
- J.M. Langer,
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  Institute of Physics Conference Series, Vol. 135, pp. 197-206, 1994.
- L. Lavagno and A. Sangiovanni-Vincentelli,
  "Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits",
  Proc. International Conf. Computer Design (ICCD), IEEE Computer Society Press, pp. 275-278, October, 1992.
- L. Lavagno, N. Shenoy and A. Sangiovanni-Vincentelli,
  "Linear Programming for Hazard Elimination in Asynchronous Circuits",
  Journal of VLSI Signal Processing, Vol. 7, No. 1/2, pp. 137-160, February, 1994.
- L. Lavagno, K. Keutzer and A. Sangiovanni-Vincentelli,
  "Synthesis of Hazard-Free Asynchronous Circuits with Bounded Wire Delays",
  IEEE Transactions on Computer-Aided Design, Vol. 14, No. 1, pp. 61-86, January, 1995.
- A.M. Liapunov,
  "Stability of motion",
  Academic Press, 1966.
- Y.W. Lim and J.R. Cox,
  "Clocks and the performance of synchronisers",
  IEE Proceedings, Part E, Computers and Digital Techniques, Vol. 130, No. 2, pp. 57-64, March, 1983.
- W.M. Littlefield and T.J. Chaney,
  "The Glitch Phenomenon",
  Technical Memo No. 10, Washington University, 1966.
- P.B. Littlewood,
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- S. Lubkin,
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  PhD thesis, Leningrad Electrical Engineering Institute, Leningrad, 224 pages, 1986.
  (Scanned 32MB PDF in Russian available on request)
- R. Manner,
  "Metastable states in asynchronous digital systems - avoidable or unavoidable",
  Microelectronics and Reliability, Vol. 28, No. 2, pp. 295-307, 1988.
- P. Marchgay, et al,
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  Proc. 3rd Int. Conf. Reliability and Maintainability, pp. 663-667, 1982.
- L.R. Marino,
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  IEEE Transactions on Computers, Vol. 26, No. 11, pp. 1082-1090, November, 1977.
- L.R. Marino,
  "General Theory of Metastable Operation",
  IEEE Transactions on Computers, Vol. C-30, No. 2, pp. 107-115, February, 1981.
- L.R. Marino,
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  Computer Science Press, Rockwell, 1986.
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- C. Mead and L. Conway,
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  Addison-Wesley, ISBN 0-201-04358-0, October, 1988.
  [notes: Sections 1.14, 7.5, 9.6]
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  Masters Thesis, Lehigh University, 1992.
  [notes: 104 pages]
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- I. Mitchell and M. Greenstreet,
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  Masters thesis, University of British Colombia, 1996.
- L. Morin and H.F. Li,
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- F. Mu, C. Svensson,
  "High speed interface for system-on-chip design by self-tested self-synchronization",
  ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI, IEEE. Vol. 2, pp.516-519, June, 1999.
  [Abstract: Global synchronization has been commonly used to protect clocked I/O from data read failure due to metastability. For future high performance system-on-chip design, global synchronization is more difficult as both frequency and chip size increase quickly. This paper addresses a mesochronous clocking (MC) strategy which can be implemented with three self-tested self-synchronization (STSS) methods for parallel data transfer between processing elements (PEs). Compared with global synchronization, MC has many advantages: lower process cost; less power dissipation in clock distribution; no limit in system scale; less delay in long distance data transfer; more simplicity and flexibility in design. The STSS implementations are also very simple and robust, and the metastability in data read is avoided because STSS is completely insensitive to both clock skew and data delay.]
- F. Mu, C. Svensson,
  "Self-tested self-synchronization circuit for mesochronous clocking",
  IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, Vol. 48, No. 2, pp. 129-140, February, 2001.
  [Abstract: In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6- mu m CMOS. Comparison is made between STSS-1 and STSS-3.]
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P
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  Technical Report CS-TR-789, School of Computing Science, University of Newcastle upon Tyne, UK, January, 2003.
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  Technical Report CS-TR-859, School of Computing Science, University of Newcastle upon Tyne, UK, September, 2004.
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Q
R
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  Proceedings VIPromCom-2001. 3rd International Symposium on Video Processing and Multimedia Communications. Croatian Soc. Electron. Marine - ELMAR. Zadar, Croatia, pp. 225-228, June, 2001. [Abstract: We discuss the issues relating to the metastability performance of clocked FIFO in asynchronous system applications. The idea of synchronizing the status flags of clocked FIFO is analysed. We show the equations used to calculate metastable failure rate and determine metastability parameters for one-stage and two-stage synchronization. The results of determining the metastability failure rate of D-type flip-flop synchronizers are given.]
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S
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  [Abstract: In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure do to metastability. Synchronous design style is widely used, easy to grasp and to implement, also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous design style (GUM-design-style) is to overcome these drawbacks by identifying and allowing all single and bidirectional high-speed signal links needed, while still retaining the simplicity uncomplicated implementation and tool support. In this paper GUM-design-style is described, analysed and demonstrated. Experimental results from a large-scale high-speed system using three 0.8 mu m BiCMOS chips are given. GUM-design-style is scaleable and suitable for future System on Chip (SoC) both on and between chips.]
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T
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U
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V
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W
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  [Abstract: This paper presents a method for evaluating the metastability of a flip-flop circuit for random number generation applications. It is well known that digital circuits can exhibit metastable behavior when the input to a flip-flop is asynchronous to the system clock. In the past, extensive research has been focused on eliminating metastability in digital systems. Here, we present some preliminary results of our research to exploit metastable behavior in sequential logic circuits to produce random bit streams for random number generation. In particular, we explore the idea of tapping the electronic noise present in D-type flip-flops to produce random bit streams for use as a one-time cryptographic key-pad for encryption algorithms. This research will serve as a basis for further research into the very-large-scale-integration (VLSI) of random number generators (RNGs).]
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  [Abstract: Traditional synchronization methodologies have largely concentrated on the use of a global clock signal to maximize the functional integration possible on the chip. Unfortunately, distribution of a low skew clock signal over the entire die at current clock rates is becoming increasingly difficult. By using a combination of architectural design and delay insensitive data encoding, it is possible to ameliorate the inter-patch penalties and take synchronization overhead into account. Extending this architectural modeling, it is also possible to account for other types of overhead, such as those due to Vdd changes between digital regions and analog or RF regions, thus enabling design optimizations for system on a chip applications. Finally, a potential methodology for containing metastability at synchronizer boundaries with relatively low latencies is proposed.]
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X
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  Technical Report TR627, Dept. of Computing Science, University of Newcastle upon Tyne, January, 1998.
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  Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000). IEEE Comput. Soc. pp. 150-159, April, 2000.
  [Abstract: Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that these VLSI solutions are more robust with regard to steering logic metastability, and can potentially run faster than solutions under fundamental mode assumptions. They are therefore more suitable for use in on-chip multiprocessing systems.]
Y
- A.V. Yakovlev, L. Lavagno and A. Sangiovanni-Vincentelli,
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  Masters Thesis, Washington University, 1990.
  [notes: 120 pages]
- J.M. Yarbrough,
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  Pub. unknown, ISBN 0-314-06675-6, 1996.
  [notes: Section 5.3.3, pp. 268-271].
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Z
- J. Zhou, D.J. Kinniment, G. Russell, and A. Yakovlev,
  "A Robust Synchronizer",
  Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI�06). pp. 442-443, March 2006.
  [Absract: We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can more than maintain the value of the metastability time constant, τ, without significantly increasing the power. Our circuit also reduces the variation of τ with Vdd and temperature, so that it has a lower τ at 50% Vdd than the conventional jamb latch has at 60% Vdd.]
  http://www.async.org.uk/David.Kinniment/Research/papers/ISVLSI.pdf
- Zhou J, Kinniment DJ, Dike C, Russell G, Yakovlev A.
  "On-chip measurement of deep metastability in synchronizers".
  IEEE Journal of Solid-State Circuits 2008, 43(2), 550-557.

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