Troubleshooting Vanilla VHDL

Error Example Possible Cause Fix
Any Vanilla command
Bad command or file name Bad command or file name  Command mistyped, or PATH not set (e.g. VANILLA not run yet). Check spelling of command. If OK, check PATH includes the VANILLA directory.
va87 

H:\PATH>va87 file.vhd

block/generate label required 
(in config)
**** ERROR foo.vhd, line n **** 
USE ENTITY WORK.entity(arch); 
**** ERROR comp: block/generate 
     label required. 
No instance of component given in FOR ... USE statement. Make sure component included and check spelling.
Component name not found **** ERROR foo.vhd, line n **** 
BarOne:Bar 
**** ERROR bar: not found 
**** ERROR foo.vhd, line m **** 
         Port => Sig); 
**** ERROR Component name not found 
Component named Bar not declared in this architecture Check spelling of Bar, and check it is declared.
Design unit load failure [With e.g. a CONFIGURATION, USE statement, or simulation] 
**** ERROR Design unit load 
      failure: work.foo 
Unit foo not yet analyzed into libary work, or analyzed out of sequence. Analyse file containing foo, and then analyze file.vhd again.
Formal has illegal actual. **** ERROR foo.vhd, line n **** 
      PortA <= Sig); 
**** ERROR Formal PortA has illegal actual. 
Problem with `actual' parameter in function, port map, generic, etc. Check format of `actual' parameter passed
Illegal signal assignment **** ERROR foo.vhd, line n **** 
Sig <= value; 
**** ERROR Illegal signal assignment. 
Attempt to assign to an write-only signal (e.g. Sig is an IN port) Fix declaration of Sig or assign to a different signal
Label mismatch 
[after END]
**** ERROR foo.vhd, line n **** 
END Fie; 
**** ERROR Label mismatch: (fee, fie). 
Label after END misspelled or mismatched. Correct spelling and match of beginning and ending labels.
must be re-analyzed [When e.g. a CONFIGURATION or running 
vs87 work.foo] ERROR: H:\PATH\WORK.foo must be re-analyzed 
due to newer version of H:\PATH\WORK.bar. 
Unit foo depends on bar, but has not been re-analyzed since the last time bar was analyzed. Analyse file containing foo, and then analyze file.vhd again. [Files depending on foo may also need re-analyzing.]
Need whitespace ... **** ERROR foo.vhd, line n **** 
y <= a AND b AFTER 7ns; 
**** ERROR Need whitespace between abstract literals and identifiers. 
No space between number and identifier ("7" and "ns" here). Insert space so it becomes e.g. "7 ns".
not found **** ERROR foo.vhd, line n **** 
PORT (A, B : IN Name; 
**** ERROR name: not found 
Type, Component, etc. Name not declared or analyzed Check spelling of Name and check it is analyzed.
no such port [config file] **** ERROR foo.vhd, line n **** 
END FOR; 
**** ERROR y: no such port. 
The component and entity ports do not match. Check this comp is configured to use the correct entity.
object not writable **** ERROR foo.vhd, line n **** 
Sig := Expression; 
**** ERROR sig: object not writable. 
Sig is a signal, not a variable Check declaration of Sig; use <= assignment if signal
Open failed Open failed for file.vhd.  File doesn't exist. Check file.vhd exists, and is spelt correctly.
Open failure for library ERROR: Open failure for library work (work): Unknown error  No work library directory. Use mkvlib work to make the work library directory.
Static association required 
[in PORT MAP]
**** ERROR foo.vhd, line n **** 
PORT MAP (Name <= Sig, 
**** ERROR Static association required for name. 
Problem with association of ports with signals (here bad use of "<=") Make sure port map associations are of the form Name => Sig 
syntax error 
[in TYPE declaration]
**** ERROR foo.vhd, line n **** 
TYPE SomeType IS (0, 1, X, Z); 
**** ERROR foo.vhd, line n **** 
near "0":syntax error 
Integers like 0 or 1 can't be used in user-defined enumerated types. Use character constants `0', `1', `X', `Z' instead.
syntax error 
[at `=']
**** ERROR foo.vhd, line n **** 
Name = Expression; 
**** ERROR foo.vhd, line n **** 
near "=":syntax error 
Use of = instead of <= or := assignments Use <= if Name is a signal, or := if a variable
syntax error 
[at start of line]
**** ERROR foo.vhd, line n **** 
Sig <= 0; 
**** ERROR foo.vhd, line n **** 
near "Sig":syntax error 
The word Sig is not declared: perhaps misspelled? Check spelling and declaration of Sig.
syntax error 
[at start of line]
**** ERROR foo.vhd, line n **** 
FirstWord Token ... 
**** ERROR foo.vhd, line n **** 
near "FirstWord":syntax error 
If FirstWord is OK, error at end of previous line likely, e.g. missing ";", BEGIN, IS, etc. Check and correct previous line
syntax error 
[at EOF (end of file)]
**** ERROR foo.vhd, line n **** 
**** ERROR foo.vhd, line n **** 
near "EOF":syntax error 
Something missing from the end of the file, e.g. END Something;  Check last unit in file (e.g. ARCHITECTURE) has matching END
syntax error 
[at IS]
**** ERROR foo.vhd, line n **** 
COMPONENT Bar IS 
**** ERROR foo.vhd, line n **** 
near "is":syntax error 
Component declarations don't use IS Delete "IS"
syntax error 
[after END]
**** ERROR foo.vhd, line n **** 
END Name; 
**** ERROR foo.vhd, line n **** 
near "name":syntax error 
Incorrect format of END of e.g. COMPONENT or FOR Use e.g. 

END COMPONENT or END FOR 

(without Name)

syntax error 
[at FOR]
**** ERROR foo.vhd, line n **** 
FOR label:comp 
**** ERROR foo.vhd, line n **** 
near "for":syntax error 
Bad nesting of FORs in configuration file. Check structure of configuration.
Type mismatch 
[in WAIT statement]
**** ERROR foo.vhd, line n **** 
WAIT UNTIL m ns; 
**** ERROR Type mismatch. 
Confusion between WAIT FOR, WAIT ON and WAIT UNTIL Ensure types are: 
WAIT FOR Time 
WAIT ON Signal 
WAIT UNTIL Test
Unknown component declaration [config file] **** ERROR foo.vhd, line n **** 
USE ENTITY WORK.ent(arch); 
**** ERROR Unknown component declaration. 
The component in 
"FOR label:comp" before this line is not declared
Check spelling of component "comp", and that it is declared.
vs87
Usage: H:\PATH>vs87 foo 
[...] 
Usage: vs87 [options] library.primary_unit[(secondary_unit)] 
No library name given. Try using: vs87 work.foo 
Open failure for library H:\PATH>vs87 foo.bar 
[...] 
ERROR: Open failure for library foo (foo): Unknown error 
Library foo doesn't exist. Check library spelt correctly and directory exists. Check mappings in vanilla.ini.
not found C:\PATH>vs87 work.foo 
[...] 
ERROR: C:\PATH\WORK.foo not found 
Unit foo doesn't exist in library work. Check spelling of foo. Use vls work to list units in libary: analyze foo if necessary.
Warning: Unbound component -- Warning: Unbound component: gate1  Configuration incomplete: perhaps simulating entity instead of config? Check correct config given to vs87. Check component gate1 is configured.
vtab
No such file or directory H:\PATH>vtab 
van.log: No such file or directory 
No trace output. Use trace command next time vs87 is run
M D Plumbley, Division of Engineering, King's College London
Last updated 8/5/98 (HTML IGC)